Field of the Invention
The invention relates to fields of non-volatile memory, and more particularly, to a read/write control device of resistive type memory. The resistive type memory is a memory comprising elements that may change resistance characteristics thereof according to directional changes of currents flowing therethrough, such as magnetic random access memory (MRAM) or resistive random access memory (RRAM or ReRAM).
Descriptions of the Related Art
Resistive type memory is a non-volatile memory, which may store data through the use of its resistance characteristic. Particularly, MRAM is a resistive type memory, which is primarily composed of magnetic tunnel junction (MTJ) structures, using electron spin characteristic thereof and changes of magnetic orientations in free layers of magnetic structures to make resistance changes so as to record data “0” and “1”.
A basic core memory bit cell of the above MRAM comprises one MTJ element and one switch transistor. The MTJ element acts as a variable resistance. This means, whether to write data “1” or “0” to the memory bit cell depends on a current flow direction through the MTJ element. For example, if the current flows from a bit line (BL) to a source line (SL), it would decrease the resistance of the MTJ element and thus data “0” is being written. If the current flows from SL to BL, it would increase the resistance of the MTJ element and thus data “1” is being written.
FIG. 1A is a schematic diagram showing the architecture of a conventional read/write circuit of resistive type memory. As shown in FIG. 1A, the circuit architecture comprises: an address decoder 11, a SL driving circuit 12, a BL driving circuit 13, and a read detection unit 14 having a current sense amplifier (SA), so as to perform read/write control on a memory bit cell on a particular row and a particular column of a memory bit cell array 10. The address decoder 11 outputs column selection signals CS0b-CSnb and CS0-CSn to a SL selection multiplexer set 140 and a BL selection multiplexer set 141 respectively, wherein each selection multiplexer of the SL selection multiplexer set 140 and BL selection multiplexer set 141 is composed of PMOS and NMOS connected in parallel to each other. The address decoder 11 controls which selection multiplexer and which word line to be turned on, so as to select a memory bit cell to perform read/write operations thereon. It should be noted that, in response to a voltage signal to be transmitted including high level signal (such as power signal VDD) and low level signal (such as ground signal GND), the multiplexer is, but not limited to, in the form of parallel-connected PMOS and NMOS as in FIG. 1A. However if the voltage signal to be transmitted is only required to be below VDD-Vth, the multiplexer may be composed of a single NMOS. Flexible configuration is allowed for the multiplexer according to the embodiment being chosen.
If it is to write data “0” to a particular memory bit cell being selected, a current flows from a power terminal (that is, power signal VDD) of the BL driving circuit 13 through a PMOS transistor of the BL driving circuit 13, then through a global BL and a certain selection multiplexer of the BL selection multiplexer set 141, then through the selected memory bit cell (selection can be made via word lines WL0-WLm outputted from a word line driving circuit 15 and the above column selection signals), then through a certain selection multiplexer of the SL selection multiplexer set 140, finally through a global SL to the SL driving circuit 12 where the current flows through a NMOS transistor to a ground terminal (that is, ground signal GND); this is a current path WP0 for writing data “0” as shown in FIG. 1A. On the other hand, if it is to write data “1” to a particular memory bit cell being selected, a current flows from a power terminal (that is, power signal VDD) of the SL driving circuit 12 through a PMOS transistor of the SL driving circuit 12, then through a certain selection multiplexer of the SL selection multiplexer set 140 and the selected memory bit cell, then through a certain selection multiplexer of the BL selection multiplexer set 141, finally to the BL driving circuit 13 where the current flows through a NMOS transistor to a ground terminal; this is a current path WP1 for writing data “1” as shown in FIG. 1B. Moreover, FIG. 1C shows a current path RP for performing a read operation on a memory bit cell located on a particular row and a particular column. If it is to read data stored in a particular memory bit cell, a SL connected to this memory bit cell should go through a certain selection multiplexer of the SL selection multiplexer set 140 to reach a global SL and then through a NMOS transistor to a ground terminal. And, a bit line connected to the memory bit cell should go through a certain selection multiplexer of the BL selection multiplexer set 141 to reach a global BL and then to be connected to an input terminal of SA. The current paths WP0 and WP1 from the power terminal to the ground terminal must at least pass through two PMOS transistors and two NMOS transistors. If the BL selection multiplexer set 141 and the SL selection multiplexer set 140 use more than two transistors to be connected in series, or the design of the SL driving circuit 12 and BL driving circuit 13 is more complicated, the current paths may need to pass through even more MOS transistors.
Take MRAM as an example, a write current for a MTJ element of size 100 nm is greater than 600 μA. The more transistors the current paths WP0 and WP1 pass through, the larger the size of each transistor must be in order to provide a required current strength. Particularly, if each multiplexer of the BL selection multiplexer set 141 is changed from having one transistor to two serially connected transistors, these two transistors must be each enlarged to be twice of its original size to have intact current drive capability. Such enlargement undesirably increases parasitic capacitance on the read/write paths and thus increases current consumption, thereby even reducing read/write speed of the memory.
Therefore, how to make a new read/write circuit of resistive type memory in order to solve the above problems of the conventional technology is an important topic in the art.